Compiler for a command-aware hardware architecture

In an embodiment, a compiler for generating command bundles is configured to receive an execution definition that includes operations for execution. The compiler determines an ordered set of hardware functions corresponding to a hardware architecture to execute at least one operation. The hardware a...

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Bibliographic Details
Main Authors Lakshminarasimhan, Srikanth, Lu, Jui-Yang, Sabato, Simon Luigi, Shah, Jay
Format Patent
LanguageEnglish
Published 07.06.2022
Subjects
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
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Summary:In an embodiment, a compiler for generating command bundles is configured to receive an execution definition that includes operations for execution. The compiler determines an ordered set of hardware functions corresponding to a hardware architecture to execute at least one operation. The hardware architecture may be selected from typical processor types or a command-aware hardware processor. The compiler generates a command bundle that includes a set of logically independent commands based on hardware functions and functionality of the hardware architecture to optimize execution of the operations. A command-aware hardware processor includes a hardware routing mesh that includes sets of routing nodes that form one or more hardware pipelines. Many hardware pipelines may be included in the hardware routing mesh. A command bundle is transmitted through a selected hardware pipeline via a control path, and is modified by the routing nodes based on execution of commands to achieve a desired outcome.
Bibliography:Application Number: US202117145662