Processor system having memory interleaving, and method for accessing interleaved memory banks with one clock cycle

A processor system comprises a memory having at least two interleaved memory banks, at least two multiplexers which are respectively coupled to one of the at least two interleaved memory banks via a respective memory bank bus, a first processor or processor core which is coupled to first multiplexer...

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Bibliographic Details
Main Authors Freitag, Johannes, Uhrig, Sascha
Format Patent
LanguageEnglish
Published 31.05.2022
Subjects
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
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Summary:A processor system comprises a memory having at least two interleaved memory banks, at least two multiplexers which are respectively coupled to one of the at least two interleaved memory banks via a respective memory bank bus, a first processor or processor core which is coupled to first multiplexer inputs of the at least two multiplexers via a first data bus, a second processor or processor core which is coupled to second multiplexer inputs of the at least two multiplexers via a second data bus, and at least two queue buffers which are arranged in the second data bus between the second processor or processor core and the second multiplexer inputs of the at least two multiplexers. The first processor or processor core is configured to have read access or write access only to one of the at least two interleaved memory banks within one clock cycle.
Bibliography:Application Number: US202017018470