Semiconductor processing system with in-situ electrical bias and methods thereof

A method of fabricating a semiconductor device includes placing a semiconductor wafer into a processing chamber, the semiconductor wafer including a first conductive layer and a second conductive layer separated by an intermediate layer; applying an electrical bias voltage across the intermediate la...

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Main Authors Domsa, Ioan, Van Der Linde, Gerhardus, Clarke, Barry, Burel, Maciej, Ragnarsson, Lars-Ake, Hurley, David, Popovici, Mihaela Ioana, Colgan, Ian, Hughes, Patrick
Format Patent
LanguageEnglish
Published 17.05.2022
Subjects
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
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Summary:A method of fabricating a semiconductor device includes placing a semiconductor wafer into a processing chamber, the semiconductor wafer including a first conductive layer and a second conductive layer separated by an intermediate layer; applying an electrical bias voltage across the intermediate layer by coupling the first conductive layer to a first potential and coupling the second conductive layer to a second potential; and annealing the semiconductor wafer while applying the electrical bias voltage.
Bibliography:Application Number: US202016841342