Enhancement mode III-nitride devices having an Al1-xSixO gate insulator
A transistor includes a III-N channel layer; a III-N barrier layer on the III-N channel layer; a source contact and a drain contact, the source and drain contacts electrically coupled to the III-N channel layer; an insulator layer on the III-N barrier layer; a gate insulator partially on the insulat...
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Main Authors | , , , , , , , |
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Format | Patent |
Language | English |
Published |
03.05.2022
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Subjects | |
Online Access | Get full text |
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Summary: | A transistor includes a III-N channel layer; a III-N barrier layer on the III-N channel layer; a source contact and a drain contact, the source and drain contacts electrically coupled to the III-N channel layer; an insulator layer on the III-N barrier layer; a gate insulator partially on the insulator layer and partially on the III-N channel layer, the gate insulator including an amorphous Al1-xSixO layer with 0.2<x<0.8; and a gate electrode over the gate insulator, the gate electrode being positioned between the source and drain contacts. |
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Bibliography: | Application Number: US201716070238 |