Electrostatic discharge with parasitic compensation

A circuit for preventing failure of a device includes a first rail, electrostatic discharge (ESD) protection circuitry, a second rail, an ESD switching circuitry, biasing circuitry, and a signal limiter. The first rail is for one or more first electrical components formed in a first portion of a sub...

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Bibliographic Details
Main Author Glaser, Ulrich
Format Patent
LanguageEnglish
Published 26.04.2022
Subjects
BASIC ELECTRIC ELEMENTS
CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
GENERATION
SEMICONDUCTOR DEVICES
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Summary:A circuit for preventing failure of a device includes a first rail, electrostatic discharge (ESD) protection circuitry, a second rail, an ESD switching circuitry, biasing circuitry, and a signal limiter. The first rail is for one or more first electrical components formed in a first portion of a substrate. The second rail is for one or more second electrical components formed in a second portion of the substrate. The first portion of the substrate forms an emitter of a parasitic transistor and the second portion of the substrate forms a collector of the parasitic transistor. The biasing circuitry is configured to output a bias voltage at the emitter of the parasitic transistor when the ESD switching circuitry is switched on. The signal limiter electrically couples to the first rail and the emitter of the parasitic transistor.
Bibliography:Application Number: US201916526627