Approach to bottom dielectric isolation for vertical transport fin field effect transistors

A vertical transport fin field effect transistor (VT FinFET), including one or more vertical fins on a surface of a substrate, an L-shaped or U-shaped spacer trough on the substrate adjacent to at least one of the one or more vertical fins, and a gate dielectric layer on the sidewalls of the at leas...

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Bibliographic Details
Main Authors Pranatharthiharan, Balasubramanian, Devarajan, Thamarai S, Bi, Zhenxing, Sankarapandian, Muthumanickam, Mehta, Sanjay C
Format Patent
LanguageEnglish
Published 12.04.2022
Subjects
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
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Summary:A vertical transport fin field effect transistor (VT FinFET), including one or more vertical fins on a surface of a substrate, an L-shaped or U-shaped spacer trough on the substrate adjacent to at least one of the one or more vertical fins, and a gate dielectric layer on the sidewalls of the at least one of the one or more vertical fins and the L-shaped or U-shaped spacer trough.
Bibliography:Application Number: US202016799237