Multi-layer barrier for CMOS under array type memory device and method of making thereof

A semiconductor structure includes a doped semiconductor material portion, a metal-semiconductor alloy portion contacting the doped semiconductor material portion, a device contact via structure in direct contact with the metal-semiconductor alloy portion, and at least one dielectric material layer...

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Bibliographic Details
Main Author Amano, Fumitaka
Format Patent
LanguageEnglish
Published 05.04.2022
Subjects
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
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Summary:A semiconductor structure includes a doped semiconductor material portion, a metal-semiconductor alloy portion contacting the doped semiconductor material portion, a device contact via structure in direct contact with the metal-semiconductor alloy portion, and at least one dielectric material layer laterally surrounding the device contact via structure. The device contact via structure includes a barrier stack and a conductive fill material portion. The barrier stack includes at least two metal nitride layers and at least one nitrogen-containing material layer containing nitrogen and an element selected from silicon or boron.
Bibliography:Application Number: US202016860358