Device, system and method to float a decoder for deselected address lines in a three-dimensional crosspoint memory architecture

• Main Authors: Kau, DerChang, Taub, Mase J, Srinivasan, Balaji
• Format: Patent
• Language: English
• Published: 15.03.2022
• Subjects: INFORMATION STORAGE; PHYSICS; STATIC STORES

A method, apparatus and system to address memory cells in a memory array that includes address lines comprising wordlines (WLs) and bitlines (BLs). The method comprises: controlling a decoder circuitry of a memory array, the memory array including a plurality of WLs and a plurality of BLs, the decoder circuitry including a plurality of switches coupled respectively to the WLs, or respectively to the BLs; and causing a selected switch of the plurality of switches to change a bias of a corresponding selected address line coupled thereto from a floating bias at an idle state of the decoder circuitry to either a positive bias or a negative bias without changing a bias at deselected address lines corresponding to deselected switches of the plurality of switches from the floating bias at the idle state.