Test architecture for die to die interconnect for three dimensional integrated circuits

A die-to-die repeater circuit includes a transmit circuit coupled to a die-to-die interconnect, the transmit circuit including at least one flip flop to function as a part of a linear feedback shift register (LFSR) to transmit a value across the die-to-die interconnect for design for test (DFT) to c...

Full description

Saved in:
Bibliographic Details
Main Authors Chakravarty, Sreejit, Tan, Terrence Huat Hin, Sanghani, Amit, B. S., Adithya, Sinha, Anubhav, Badana, Sudheer V, Kandula, Rakesh, Su, Fei, Lim, Wei Ming, Gupta, Puneet
Format Patent
LanguageEnglish
Published 22.02.2022
Subjects
BASIC ELECTRIC ELEMENTS
BASIC ELECTRONIC CIRCUITRY
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
INFORMATION STORAGE
PHYSICS
PULSE TECHNIQUE
SEMICONDUCTOR DEVICES
STATIC STORES
Online AccessGet full text

Cover

More Information
Summary:A die-to-die repeater circuit includes a transmit circuit coupled to a die-to-die interconnect, the transmit circuit including at least one flip flop to function as a part of a linear feedback shift register (LFSR) to transmit a value across the die-to-die interconnect for design for test (DFT) to check proper operation of the die-to-die interconnect, and a receive circuit coupled to the die-to-die interconnect, the receive circuit including at least one flip flop to function as part of a multiple input shift register (MISR).
Bibliography:Application Number: US201715717721