Shift-register circuit, gate-driving circuit, and array substrate of a display panel

The present application discloses a shift-register circuit configured as one of a plurality of shift-register units cascaded in series. The shift-register circuit includes a pull-up sub-circuit coupled to a pull-up node, a first clock port, and an output port. The pull-up sub-circuit is configured t...

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Bibliographic Details
Main Authors Zhao, Jingpeng, Hu, Shuang, Tang, Xiuzhu, Tang, Taoliang, Qian, Qian, Xiong, Lijun, Liang, Xuebo, Chen, Shuai, Dong, Xing, Tian, Zhenguo
Format Patent
LanguageEnglish
Published 08.02.2022
Subjects
ADVERTISING
ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICESUSING STATIC MEANS TO PRESENT VARIABLE INFORMATION
CRYPTOGRAPHY
DISPLAY
EDUCATION
INFORMATION STORAGE
PHYSICS
SEALS
STATIC STORES
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Summary:The present application discloses a shift-register circuit configured as one of a plurality of shift-register units cascaded in series. The shift-register circuit includes a pull-up sub-circuit coupled to a pull-up node, a first clock port, and an output port. The pull-up sub-circuit is configured to pass a first clock signal from the first clock port to the output port when the pull-up node is set to a turn-on voltage. Additionally, the shift-register circuit includes a chamfering sub-circuit coupled to the pull-up node, the first clock port, a chamfering clock port, and the output port. The chamfering sub-circuit is configured to pass a chamfering clock signal from the chamfering clock port to the output port. The chamfering clock signal is at the turn-on voltage simultaneously with the first clock signal and becomes a turn-off voltage slightly earlier in time than the first clock signal.
Bibliography:Application Number: US201716073028