Power state aware scan frequency

A system can include a memory device and a processing device to perform operations that include performing a block family calibration scan of the memory device, wherein the calibration scan comprises a plurality of scan iterations, wherein each scan iteration is initiated in accordance with a scan f...

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Bibliographic Details
Main Author Rayaprolu, Vamsi Pavan
Format Patent
LanguageEnglish
Published 11.01.2022
Subjects
INFORMATION STORAGE
PHYSICS
STATIC STORES
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Summary:A system can include a memory device and a processing device to perform operations that include performing a block family calibration scan of the memory device, wherein the calibration scan comprises a plurality of scan iterations, wherein each scan iteration is initiated in accordance with a scan frequency, and wherein each scan iteration comprises detecting a transition associated with the memory device from a first power state to a second power state, responsive to detecting the transition from the first power state to the second power state, determining an updated value of the scan frequency in view of the second power state, wherein one or more subsequent scan iterations are initiated in accordance with the updated value of the scan frequency, and performing one or more block family calibration operations.
Bibliography:Application Number: US202017125902