Error handling optimization in memory sub-system mapping

A system includes a memory device having blocks of memory cells. A processing device is operatively coupled to the memory device, the processing device to detect an error event triggered within a source block of the memory cells. In response to detection of the error event, the processing device is...

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Bibliographic Details
Main Author Lam, Johnny A
Format Patent
LanguageEnglish
Published 28.12.2021
Subjects
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
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Summary:A system includes a memory device having blocks of memory cells. A processing device is operatively coupled to the memory device, the processing device to detect an error event triggered within a source block of the memory cells. In response to detection of the error event, the processing device is to read data from the source block; write the data into a mitigation block that is different than the source block; and replace, in a block set map data structure, a first identifier of the source block with a second identifier of the mitigation block. The block set map data structure includes block location metadata for a data group, of the memory device, that includes the data.
Bibliography:Application Number: US202016912397