Data and clock synchronization and variation compensation apparatus and method

• Main Authors: Navaratnam, Navindra, Kurd, Nasser A, El-Husseini, Ali M, Teng, Bee Min, Chong, Raymond, Chowdhury, Nasirul I
• Format: Patent
• Language: English
• Published: 23.11.2021
• Subjects: BASIC ELECTRIC ELEMENTS; BASIC ELECTRONIC CIRCUITRY; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR; ELECTRICITY; INFORMATION STORAGE; PHYSICS; PULSE TECHNIQUE; SEMICONDUCTOR DEVICES; STATIC STORES

An apparatus is provided for mitigating uncertainties in process, voltage, random, and systematic variations between first and second dies. The first die comprises a clock compensator to adjust one or more signal characteristics of an input clock, and to provide first and second clocks; a data transmitter to sample data with a version of the first clock and to transmit the sampled data to a data receiver of the second die, wherein the data receiver is to receive the sampled data and generate a received data; and a clock transmitter to transmit the second clock to a clock receiver of the second die, wherein the clock receiver is to generate a third clock, wherein a phase of the third clock is adjusted to generate a fourth clock, wherein a delayed version of the fourth clock is received by a sampler coupled to the data receiver to sample the received data.