Computational array microprocessor system using non-consecutive data formatting

A microprocessor system comprises a computational array and a hardware data formatter. The computational array includes a plurality of computation units that each operates on a corresponding value addressed from memory. The values operated by the computation units are synchronously provided together...

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Bibliographic Details
Main Authors McGee, William, Talpes, Emil, Bannon, Peter Joseph
Format Patent
LanguageEnglish
Published 26.10.2021
Subjects
BASIC ELECTRONIC CIRCUITRY
CALCULATING
COMPUTER SYSTEMS BASED ON SPECIFIC COMPUTATIONAL MODELS
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
ELECTRICITY
IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS
PHYSICS
RESONATORS
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Summary:A microprocessor system comprises a computational array and a hardware data formatter. The computational array includes a plurality of computation units that each operates on a corresponding value addressed from memory. The values operated by the computation units are synchronously provided together to the computational array as a group of values to be processed in parallel. The hardware data formatter is configured to gather the group of values, wherein the group of values includes a first subset of values located consecutively in memory and a second subset of values located consecutively in memory. The first subset of values is not required to be located consecutively in the memory from the second subset of values.
Bibliography:Application Number: US201815920173