1T-1R architecture for resistive random access memory

• Main Authors: Ellis, Wayne Frederick, Sekar, Deepak Chandra
• Format: Patent
• Language: English
• Published: 19.10.2021
• Subjects: INFORMATION STORAGE; PHYSICS; STATIC STORES

A memory device comprises: an array of memory cells arranged in a plurality of columns in a first direction and a plurality of rows in a second direction, wherein each memory cell in the array comprises: a select transistor, wherein a source terminal of the select transistor is coupled to a source line, and wherein a gate terminal of the select transistor is coupled to a word line, and a memory element coupled in series with the select transistor, wherein a first end of the memory element is coupled to a drain terminal of the select transistor, and wherein a second end of the memory element is coupled to a bit line; and a control circuit configured to provide an unselected source line voltage to source lines of unselected memory cells before providing a selected word line voltage to a word line of a selected memory cell.