Trap layer substrate stacking technique to improve performance for RF devices

Some embodiments of the present disclosure are directed to a device. The device includes a substrate comprising a silicon layer disposed over an insulating layer. The substrate includes a transistor device region and a radio-frequency (RF) region. An interconnect structure is disposed over the subst...

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Bibliographic Details
Main Authors Tsai, Kuan-Chi, Chen, Shih-Shiung, Tsai, Wei-Kung, Chao, Chih-Ping, Cheng, Kuo-Yu
Format Patent
LanguageEnglish
Published 14.09.2021
Subjects
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
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Summary:Some embodiments of the present disclosure are directed to a device. The device includes a substrate comprising a silicon layer disposed over an insulating layer. The substrate includes a transistor device region and a radio-frequency (RF) region. An interconnect structure is disposed over the substrate and includes a plurality of metal layers disposed within a dielectric structure. A handle substrate is disposed over an upper surface of the interconnect structure. A trapping layer separates the interconnect structure and the handle substrate.
Bibliography:Application Number: US201916662391