High-density high-bandwidth static random access memory (SRAM) with phase shifted sequential read

The present disclosure relates to a structure including a read controller configured to receive a burst enable signal and a word line pulse signal, identify consecutive read operations from storage cells accessed via a word line, precharge bit lines once during consecutive, sequential reads, and hol...

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Bibliographic Details
Main Authors Hunt-Schroeder, Eric D, Patil, Akhilesh, Arsovski, Igor
Format Patent
LanguageEnglish
Published 07.09.2021
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Summary:The present disclosure relates to a structure including a read controller configured to receive a burst enable signal and a word line pulse signal, identify consecutive read operations from storage cells accessed via a word line, precharge bit lines once during consecutive, sequential reads, and hold the word line active through N−1 of the consecutive read operations, and N is an integer number of the consecutive read operations.
Bibliography:Application Number: US201916256584