Bus structure for parallel connected power switches
An apparatus includes a plurality of semiconductor switches. A first bus interconnects first terminals of the semiconductor switches in a first chain and provides a first impedance between the first terminals of switches of the first chain. A second bus interconnects second terminals of the semicond...
Saved in:
Main Authors | , , |
---|---|
Format | Patent |
Language | English |
Published |
06.07.2021
|
Subjects | |
Online Access | Get full text |
Cover
Loading…
Summary: | An apparatus includes a plurality of semiconductor switches. A first bus interconnects first terminals of the semiconductor switches in a first chain and provides a first impedance between the first terminals of switches of the first chain. A second bus interconnects second terminals of the semiconductor switches in a second chain and provides a second impedance greater that the first impedance between the second terminals of the switches of the second chain. The apparatus may be implemented as a laminated bus assembly including respective overlapping conductor plates, wherein the second bus includes a plate having subregions defined by features, such as slots or grooves, that provide the second impedance. |
---|---|
Bibliography: | Application Number: US201916599955 |