CPU cache flushing to persistent memory

A computing system having a power loss detector and memory components to store data associated with write commands received from a host system. The write commands are flushed from a protected write queue of the host system responsive to detecting an impending loss of power. The computing system furt...

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Bibliographic Details
Main Authors Mittal, Samir, Stonelake, Paul
Format Patent
LanguageEnglish
Published 25.05.2021
Subjects
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
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Summary:A computing system having a power loss detector and memory components to store data associated with write commands received from a host system. The write commands are flushed from a protected write queue of the host system responsive to detecting an impending loss of power. The computing system further includes a processing device to receive the write commands over a memory interface. The processing device is further to, responsive to detecting the loss of power by the detector: disable the memory interface, and store the data associated with write commands that are received prior to disabling the memory interface. The data is stored in one or more of the memory components using power supplied by one or more capacitors.
Bibliography:Application Number: US201816167189