Bonded structure including a performance-optimized support chip and a stress-optimized three-dimensional memory chip and method for making the same

• Main Authors: Shirasu, Tetsuya, Fukano, Yuji, Hosoda, Naohiro, Shimamoto, Kazuma, Nishida, Akio
• Format: Patent
• Language: English
• Published: 18.05.2021
• Subjects: BASIC ELECTRIC ELEMENTS; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR; ELECTRICITY; INFORMATION STORAGE; PHYSICS; SEMICONDUCTOR DEVICES; STATIC STORES

A bonded assembly includes a memory die including a three-dimensional memory array located on a first single crystalline semiconductor substrate, and a logic die including a peripheral circuitry located on a second single crystalline semiconductor substrate and bonded to the memory die. The three-dimensional memory array includes word lines and bit lines. The logic die includes field effect transistors having semiconductor channels configured to flow electrical current along a channel direction that is parallel to the bit lines or word lines. Different crystallographic orientations are used for the first and second single crystalline semiconductor substrates. The crystallographic orientations of the first single crystalline semiconductor substrate are selected to minimize stress deformation of the memory chip, while the crystallographic orientations of the second single crystalline semiconductor substrate are selected to maximize device performance of the peripheral circuitry.