High efficiency on-chip 3D transformer structure

An integrated circuit transformer structure includes at least two conductor groups stacked in parallel in different layers. A first spiral track is formed in the at least two conductor groups, the first spiral track included first turns of a first radius within each of the at least two conductor gro...

Full description

Saved in:
Bibliographic Details
Main Authors Groves, Robert A, Barry, Robert L, Vanukuru, Venkata Nr
Format Patent
LanguageEnglish
Published 18.05.2021
Subjects
Online AccessGet full text

Cover

Loading…
More Information
Summary:An integrated circuit transformer structure includes at least two conductor groups stacked in parallel in different layers. A first spiral track is formed in the at least two conductor groups, the first spiral track included first turns of a first radius within each of the at least two conductor groups, and second turns of a second radius within each of the at least two conductor groups, the first and second turns being electrically connected. A second spiral track is formed in the at least two conductor groups, the second spiral track including third turns of a third radius within each of the at least two conductor groups and disposed in a same plane between the first and second turns in each of the at least two conductor groups.
Bibliography:Application Number: US201816012384