Additional spacer for self-aligned contact for only high voltage FinFETs

A method includes forming a first region including a pair of first FinFETs and a second region including a pair of second FinFETs on a substrate. Each FinFET includes a metal gate having a first spacer adjacent thereto, and each first FinFET has a gate dielectric that is thicker than a gate dielectr...

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Bibliographic Details
Main Authors Saudari, Sangameshwar Rao, Zhao, Kai, Haran, Bala S, Zainuddin, Abu Naser M, Ma, Wei, Sheraw, Christopher D
Format Patent
LanguageEnglish
Published 27.04.2021
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Summary:A method includes forming a first region including a pair of first FinFETs and a second region including a pair of second FinFETs on a substrate. Each FinFET includes a metal gate having a first spacer adjacent thereto, and each first FinFET has a gate dielectric that is thicker than a gate dielectric of each second FinFET, such that the first FinFETs can be higher voltage input/output devices. The method forms a first contact between the metal gates of the pair of first FinFETs with a second spacer thereabout, the second spacer contacting a portion of each first spacer. The second spacer thus has a portion extending parallel to the metal gates, and a portion extending perpendicular to the metal gates. A second contact is formed between the metal gates of the pair of second FinFETs, and the second contact devoid of the second spacer.
Bibliography:Application Number: US201916376234