Streaming interconnect architecture for data processing engine array

• Main Authors: Bilski, Goran Hk, Dick, Christopher H, Vissers, Kornelis A, Langer, Jan, Ozgul, Baris, Walke, Richard L, James-Roxby, Philip B, Noguera Serra, Juan J, Wittig, Ralph D, McColgan, Peter
• Format: Patent
• Language: English
• Published: 27.04.2021
• Subjects: CALCULATING; COMPUTING; COUNTING; ELECTRIC DIGITAL DATA PROCESSING; PHYSICS

Examples herein describe techniques for communicating between data processing engines in an array of data processing engines. In one embodiment, the array is a 2D array where each of the DPEs includes one or more cores. In addition to the cores, the data processing engines can include a memory module (with memory banks for storing data) and an interconnect which provides connectivity between the engines. To transmit processed data, a data processing engine identifies a destination processing engine in the array. Once identified, the data processing engine can transmit the processed data using a reserved point-to-point communication path in the interconnect that couples the source and destination data processing engines.