System, apparatus and method for loose lock-step redundancy power management

A processor includes a plurality of cores, at least two of which may execute redundantly, a configuration register to store a first synchronization domain indicator to indicate that a first core and a second core are associated with a first synchronization domain, and a power controller having a syn...

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Bibliographic Details
Main Authors Rosenzweig, Nir, Aizik, Yoni, Rajwan, Doron, Weissmann, Eliezer, Rotem, Efraim
Format Patent
LanguageEnglish
Published 27.04.2021
Subjects
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
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Summary:A processor includes a plurality of cores, at least two of which may execute redundantly, a configuration register to store a first synchronization domain indicator to indicate that a first core and a second core are associated with a first synchronization domain, and a power controller having a synchronization circuit to cause a dynamic adjustment to a frequency of at least one of the first and second cores to cause these cores to operate at a common frequency, based at least in part on the first synchronization domain indicator.
Bibliography:Application Number: US201916663645