Fin trim isolation with single gate spacing for advanced integrated circuit structure fabrication

Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, a method includes forming a plurality of fins, individual ones o...

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Bibliographic Details
Main Authors Auth, Christopher P, Ghani, Tahir, Ho, Byron, Hattendorf, Michael L
Format Patent
LanguageEnglish
Published 20.04.2021
Subjects
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
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Summary:Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, a method includes forming a plurality of fins, individual ones of the plurality of fins along a first direction. A plurality of gate structures is formed over the plurality of fins, individual ones of the gate structures along a second direction orthogonal to the first direction. A dielectric material structure is formed between adjacent ones of the plurality of gate structures. A portion of one of the plurality of gate structures is removed to expose a portion of each of the plurality of fins. The exposed portion of each of the plurality of fins is removed. An insulating layer is formed in locations of the removed portion of each of the plurality of fins.
Bibliography:Application Number: US202016906427