Broadside random access memory for low cycle memory access and additional functions

A computational system includes one or more processors. Each processor has multiple registers, as well attached memory to hold instructions. The processor is coupled to one or more broadside interfaces. A broadside interface allows the processor to load or store an entire widget state in a single cl...

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Bibliographic Details
Main Authors Lide, David Alston, Wallace, William Cronin, Thalakkal K{dot over (o)}ttilaveedu, Pratheesh Gangadhar, Leyrer, Thomas Anton
Format Patent
LanguageEnglish
Published 06.04.2021
Subjects
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
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Summary:A computational system includes one or more processors. Each processor has multiple registers, as well attached memory to hold instructions. The processor is coupled to one or more broadside interfaces. A broadside interface allows the processor to load or store an entire widget state in a single clock cycle of the processor. The broadside interface also allows the processor to move and store 32 bytes of information into RAM in less than four to five clock cycles of the processor while the processor concurrently performs one or more mathematical operations on the information while the move and store operation is taking place.
Bibliography:Application Number: US201916424913