Low-power, low-latency time-to-digital-converter-based serial link

A receiver is provided that includes a time-to-digital converter for converting a phase difference between a clock signal and a received data signal into a phase-difference digital code. The receiver also includes a logic circuit that controls a programmable delay line to delay the clock signal into...

Full description

Saved in:
Bibliographic Details
Main Authors Hailu, Eskinder, Pandita, Bupesh, Jun, Yong Suk, Zhu, Zhi, Chen, Minhan, Goudarzi, Hadi, Boyette, Jon
Format Patent
LanguageEnglish
Published 30.03.2021
Subjects
BASIC ELECTRONIC CIRCUITRY
ELECTRIC COMMUNICATION TECHNIQUE
ELECTRICITY
HOROLOGY
PHYSICS
PULSE TECHNIQUE
TIME-INTERVAL MEASURING
TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHICCOMMUNICATION
Online AccessGet full text

Cover

More Information
Summary:A receiver is provided that includes a time-to-digital converter for converting a phase difference between a clock signal and a received data signal into a phase-difference digital code. The receiver also includes a logic circuit that controls a programmable delay line to delay the clock signal into a delayed clock signal by a delay that is responsive to a difference between the phase-difference code and a unit interval for the clock signal. The delayed clock signal clocks a flip-flop to register the received data signal.
Bibliography:Application Number: US201816150123