Low-power, low-latency time-to-digital-converter-based serial link
A receiver is provided that includes a time-to-digital converter for converting a phase difference between a clock signal and a received data signal into a phase-difference digital code. The receiver also includes a logic circuit that controls a programmable delay line to delay the clock signal into...
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Main Authors | , , , , , , |
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Format | Patent |
Language | English |
Published |
30.03.2021
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Subjects | |
Online Access | Get full text |
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Summary: | A receiver is provided that includes a time-to-digital converter for converting a phase difference between a clock signal and a received data signal into a phase-difference digital code. The receiver also includes a logic circuit that controls a programmable delay line to delay the clock signal into a delayed clock signal by a delay that is responsive to a difference between the phase-difference code and a unit interval for the clock signal. The delayed clock signal clocks a flip-flop to register the received data signal. |
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Bibliography: | Application Number: US201816150123 |