Selecting a low power state based on cache flush latency determination

In an embodiment, a processor includes a plurality of cores to independently execute instructions, a shared cache coupled to the cores and including a plurality of lines to store data, and a power controller including a low power control logic to calculate a flush latency to flush the shared cache b...

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Bibliographic Details
Main Authors Choubal, Ashish V, Durg, Ajaya V, Muthukumar, Kalyan, Ramani, Sundar, Chakki, Samudyatha, Raman, Arvind, Mandhani, Arvind
Format Patent
LanguageEnglish
Published 30.03.2021
Subjects
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
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Summary:In an embodiment, a processor includes a plurality of cores to independently execute instructions, a shared cache coupled to the cores and including a plurality of lines to store data, and a power controller including a low power control logic to calculate a flush latency to flush the shared cache based on a state of the plurality of lines. Other embodiments are described and claimed.
Bibliography:Application Number: US201916252816