Self-biased gate driver architecture

A system includes a primary field effect transistor (FET) coupled to a primary winding on a primary side of an alternating current-to-direct current (AC-DC) converter. The system also includes a gate driver, coupled to the primary FET, that is to, in response to a signal received from a startup cont...

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Bibliographic Details
Main Authors Lee, Myeongseok, Nayak, Anup, Lilamwala, Murtuza
Format Patent
LanguageEnglish
Published 09.03.2021
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Summary:A system includes a primary field effect transistor (FET) coupled to a primary winding on a primary side of an alternating current-to-direct current (AC-DC) converter. The system also includes a gate driver, coupled to the primary FET, that is to, in response to a signal received from a startup controller of the AC-DC converter, turn on the primary FET. The gate driver includes a voltage bias p-type metal-oxide-semiconductor (VBP) buffer coupled between an external supply voltage and a VBP portion of driving chain circuitry, the driving chain circuitry to drive a gate of the primary FET. The gate driver also includes a voltage bias n-type metal-oxide-semiconductor (VBN) buffer coupled between a VBN regulator, which generates an internal supply voltage, and a VBN portion of the driving chain circuitry.
Bibliography:Application Number: US202017024538