Address interleave support in a programmable device

Techniques for providing address interleave support in a programmable device are described. In an example, a programmable integrated circuit (IC) includes a processing system, programmable logic, a plurality of master circuits disposed in the processing system, the programmable logic, or both the pr...

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Bibliographic Details
Main Author Swarbrick, Ian A
Format Patent
LanguageEnglish
Published 02.03.2021
Subjects
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
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Summary:Techniques for providing address interleave support in a programmable device are described. In an example, a programmable integrated circuit (IC) includes a processing system, programmable logic, a plurality of master circuits disposed in the processing system, the programmable logic, or both the processing system and the programmable logic, an address interleave and transaction chopping circuit, a memory having a plurality of channels, and a system interconnect configured to couple the address interleave and transaction chopping circuit to the memory. The address interleave and transaction chopping circuit is configured to interleave memory transactions from the plurality of master circuits across the plurality of channels of the memory at a selected boundary.
Bibliography:Application Number: US201916282081