Optimizing memory address compression

A mechanism is described for facilitating memory address compression at computing devices. A method of embodiments, as described herein, includes coalescing slot addresses across multiple messages received from an execution unit, where the slot addresses are coalesced in groups based on memory cache...

Full description

Saved in:
Bibliographic Details
Main Authors Koker, Altug, Ray, Joydeep, Valerio, James A, Surti, Prasoonkumar, Appu, Abhishek R
Format Patent
LanguageEnglish
Published 02.02.2021
Subjects
ADVERTISING
ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICESUSING STATIC MEANS TO PRESENT VARIABLE INFORMATION
CALCULATING
COMPUTING
COUNTING
CRYPTOGRAPHY
DISPLAY
EDUCATION
ELECTRIC DIGITAL DATA PROCESSING
IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
PHYSICS
SEALS
Online AccessGet full text

Cover

More Information
Summary:A mechanism is described for facilitating memory address compression at computing devices. A method of embodiments, as described herein, includes coalescing slot addresses across multiple messages received from an execution unit, where the slot addresses are coalesced in groups based on memory cacheline addresses such that each of a set of slot addresses in a group have a memory cacheline address in common between them. The method may further include outputting the memory cacheline addresses.
Bibliography:Application Number: US201715493404