SAR ADC with variable sampling capacitor

A successive approximation register analog-to-digital converter (SAR ADC) circuit comprises N weighted bit capacitors, wherein N is a positive integer greater than one; a sampling circuit configured to sample an input voltage onto the N weighted bit capacitors; and logic circuitry. The logic circuit...

Full description

Saved in:
Bibliographic Details
Main Authors Patil, Archana, Coln, Michael C. W, Monangi, Sandeep
Format Patent
LanguageEnglish
Published 26.01.2021
Subjects
BASIC ELECTRONIC CIRCUITRY
CODE CONVERSION IN GENERAL
CODING
DECODING
ELECTRICITY
Online AccessGet full text

Cover

More Information
Summary:A successive approximation register analog-to-digital converter (SAR ADC) circuit comprises N weighted bit capacitors, wherein N is a positive integer greater than one; a sampling circuit configured to sample an input voltage onto the N weighted bit capacitors; and logic circuitry. The logic circuitry is configured to enable sampling of the input voltage onto the N weighted bit capacitors in a high-resolution mode; enable sampling of the input voltage onto N−M of the weighted bit capacitors in a low-resolution mode and sampling a common mode voltage onto the most significant M weighted bit capacitors, wherein M is a positive integer greater than zero and less than N; and initiate successive bit trials using the weighted bit capacitors to convert the sampled input voltage to a digital value.
Bibliography:Application Number: US202016791717