Flash memory bitcell erase with source bias voltage

In some examples, a flash memory comprises a first gate and a second gate located over a semiconductor substrate a third gate located between the first gate and the second gate a floating gate located between the third gate and the semiconductor substrate; and a doped region located within the semic...

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Bibliographic Details
Main Authors Bo, Xiang-Zheng, O'Brien, Corey Rollin, Vemuri, Vijaya Subramaniam
Format Patent
LanguageEnglish
Published 26.01.2021
Subjects
ELECTRICITY
INFORMATION STORAGE
PHYSICS
STATIC STORES
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Summary:In some examples, a flash memory comprises a first gate and a second gate located over a semiconductor substrate a third gate located between the first gate and the second gate a floating gate located between the third gate and the semiconductor substrate; and a doped region located within the semiconductor substrate and proximate the second gate, wherein the doped region is configured to receive a positive bias voltage with respect to the semiconductor substrate during an erase cycle.
Bibliography:Application Number: US201816230778