System and method for output voltage overshoot suppression
A method for suppressing voltage overshoot at an output of a voltage regulator is disclosed. The voltage regulator includes at least one channel having a first set of (high-side) transistors and a second set of (low-side) transistors. In implementations of the method, an output voltage at an output...
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Main Authors | , |
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Format | Patent |
Language | English |
Published |
29.12.2020
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Subjects | |
Online Access | Get full text |
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Summary: | A method for suppressing voltage overshoot at an output of a voltage regulator is disclosed. The voltage regulator includes at least one channel having a first set of (high-side) transistors and a second set of (low-side) transistors. In implementations of the method, an output voltage at an output of at least one channel of a voltage regulator is detected and compared with a reference voltage. A rate of change associated with the output voltage is also determined and compared with a threshold rate of change. When the output voltage is greater than the reference voltage and the rate of change is greater than the threshold rate of change, a resistance value associated with the second set of transistors is increased from a first resistance value to a second resistance value to prevent the output voltage from overshooting and/or to suppress an output voltage overshoot. |
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Bibliography: | Application Number: US201916254221 |