Mask process correction

Provided is a method for fabricating a semiconductor device including performing an OPC process to an IC layout pattern to generate a post-OPC layout pattern. In some embodiments, the method further includes applying an MPC model to the post-OPC layout pattern to generate a simulated mask pattern. B...

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Bibliographic Details
Main Authors Huang, Hsu-Ting, Liu, Ru-Gun
Format Patent
LanguageEnglish
Published 15.12.2020
Subjects
APPARATUS SPECIALLY ADAPTED THEREFOR
CALCULATING
CINEMATOGRAPHY
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
ELECTROGRAPHY
HOLOGRAPHY
MATERIALS THEREFOR
ORIGINALS THEREFOR
PHOTOGRAPHY
PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES,e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTORDEVICES
PHYSICS
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Summary:Provided is a method for fabricating a semiconductor device including performing an OPC process to an IC layout pattern to generate a post-OPC layout pattern. In some embodiments, the method further includes applying an MPC model to the post-OPC layout pattern to generate a simulated mask pattern. By way of example, the simulated mask pattern is compared to a mask pattern calculated from a target wafer pattern. Thereafter, and based on the comparing, an outcome of an MPC process is determined.
Bibliography:Application Number: US201916554318