Apparatus and method for an early page predictor for a memory paging subsystem

An apparatus and method for early page address prediction. For example, one embodiment of a processor comprises: an instruction fetch circuit to fetch a load instruction; a decoder to decode the load instruction; execution circuitry to execute the load instruction to perform a load operation, the ex...

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Bibliographic Details
Main Authors Zhang, Zhongying, Shevgoor, Manjunath, Guvenilir, Faruk, Dechene, Mark, Perry, Jonathan
Format Patent
LanguageEnglish
Published 08.12.2020
Subjects
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
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Summary:An apparatus and method for early page address prediction. For example, one embodiment of a processor comprises: an instruction fetch circuit to fetch a load instruction; a decoder to decode the load instruction; execution circuitry to execute the load instruction to perform a load operation, the execution circuitry including an address generation unit (AGU) to generate an effective address to be used for the load operation; and early page prediction (EPP) circuitry to use one or more attributes associated with the load instruction to predict a physical page address for the load instruction simultaneously with the AGU generating the effective address and/or prior to generation of the effective address.
Bibliography:Application Number: US201815941976