Memory systems performing reconfigurable error correction operation using ECC engine with fixed error correction capability

A memory system includes a memory medium and a memory controller. The memory medium includes data symbols and parity symbols which are respectively disposed at cross points of a plurality rows and a plurality of columns. The memory controller includes an error correction code (ECC) engine that is de...

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Bibliographic Details
Main Authors Kwon, Jung Hyun, Jeong, Seunggyu, Shin, Wongyu, Hong, Do Sun
Format Patent
LanguageEnglish
Published 24.11.2020
Subjects
BASIC ELECTRONIC CIRCUITRY
CALCULATING
CODE CONVERSION IN GENERAL
CODING
COMPUTING
COUNTING
DECODING
ELECTRIC DIGITAL DATA PROCESSING
ELECTRICITY
INFORMATION STORAGE
PHYSICS
STATIC STORES
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Summary:A memory system includes a memory medium and a memory controller. The memory medium includes data symbols and parity symbols which are respectively disposed at cross points of a plurality rows and a plurality of columns. The memory controller includes an error correction code (ECC) engine that is designed to execute an error correction operation at a fixed error correction level while the memory controller accesses the memory medium. The memory controller performs the error correction operation at the fixed error correction level using the ECC engine in a first error correction mode. The memory controller performs the error correction operation at an error correction level higher than the fixed error correction level using the ECC engine in a second error correction mode.
Bibliography:Application Number: US201816203362