Integrated circuit devices having raised via contacts and methods of fabricating the same

Methods of fabricating an integrated circuit device are provided. The integrated circuit device includes a transistor formed on a substrate. The transistor includes a source region, a drain region, and a gate structure between the source region and the drain region. The integrated circuit device als...

Full description

Saved in:
Bibliographic Details
Main Authors Chen, Jyh-Huei, Tsai, Kuo-Chiang, Cheng, Jye-Yen
Format Patent
LanguageEnglish
Published 17.11.2020
Subjects
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
Online AccessGet full text

Cover

More Information
Summary:Methods of fabricating an integrated circuit device are provided. The integrated circuit device includes a transistor formed on a substrate. The transistor includes a source region, a drain region, and a gate structure between the source region and the drain region. The integrated circuit device also includes a first dielectric layer over the transistor and a first via contact partially in the first dielectric layer and electrically connected to the source region. The integrated circuit device further includes a second via contact partially in the first dielectric layer and electrically connected to the gate structure. In addition, the upper portion of the first via contact and the upper portion of the second via contact protrude from the first dielectric layer.
Bibliography:Application Number: US201816164054