Zero test time memory using background built-in self-test

The present disclosure relates to a structure which includes a memory which is configured to enable zero test time built-in self-test (BIST) at a read/write port while concurrently performing at least one functional read operation at a read port.

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Bibliographic Details
Main Authors Hunt-Schroeder, Eric D, Ziegerhofer, Michael A, Arsovski, Igor
Format Patent
LanguageEnglish
Published 17.11.2020
Subjects
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
INFORMATION STORAGE
PHYSICS
STATIC STORES
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Summary:The present disclosure relates to a structure which includes a memory which is configured to enable zero test time built-in self-test (BIST) at a read/write port while concurrently performing at least one functional read operation at a read port.
Bibliography:Application Number: US201916520642