Hardware/software co-optimization to improve performance and energy for inter-VM communication for NFVs and other producer-consumer workloads

• Main Authors: Jaleel, Aamer, Hughes, Christopher J, Tai, Tsung-yuan C, Herdrich, Andrew J, Ergin, Mesut A, Chishti, Zeshan A, Moga, Adrian C, Venkatesan, Namakkal N, Liu, Yen-cheng, Min, Alexander W, Maciocco, Christian, Park, Jong Soo, Hum, Herbert H, Sankaran, Rajesh, Wang, Ren, Tsai, Jr-shian
• Format: Patent
• Language: English
• Published: 27.10.2020
• Subjects: CALCULATING; COMPUTING; COUNTING; ELECTRIC DIGITAL DATA PROCESSING; PHYSICS

Methods and apparatus implementing Hardware/Software co-optimization to improve performance and energy for inter-VM communication for NFVs and other producer-consumer workloads. The apparatus include multi-core processors with multi-level cache hierarchies including and L1 and L2 cache for each core and a shared last-level cache (LLC). One or more machine-level instructions are provided for proactively demoting cachelines from lower cache levels to higher cache levels, including demoting cachelines from L1/L2 caches to an LLC. Techniques are also provided for implementing hardware/software co-optimization in multi-socket NUMA architecture system, wherein cachelines may be selectively demoted and pushed to an LLC in a remote socket. In addition, techniques are disclosure for implementing early snooping in multi-socket systems to reduce latency when accessing cachelines on remote sockets.