Three-dimensional memory device having stressed vertical semiconductor channels and method of making the same

• Main Authors: Iizuka, Toshihiro, Sharangpani, Rahul, Ranganathan, Srikanth, Zhou, Fei, Rajashekhar, Adarsh, Makala, Raghuveer S, Nishida, Akio
• Format: Patent
• Language: English
• Published: 06.10.2020
• Subjects: BASIC ELECTRIC ELEMENTS; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR; ELECTRICITY; SEMICONDUCTOR DEVICES

Three-dimensional memory devices include structures that induce a vertical tensile stress in vertical semiconductor channels to enhance charge carrier mobility. Vertical tensile stress may be induced by a laterally compressive stress applied by stressor pillar structure. The stressor pillar structures can include a stressor material such as a dielectric metal oxide material, silicon nitride, thermal silicon oxide or a semiconductor material having a greater lattice constant than that of the channel. Vertical tensile stress may be induced by a compressive stress applied by electrically conductive layers that laterally surround the vertical semiconductor channel, or by a stress memorization technique that captures a compressive stress from sacrificial material layers. Vertical tensile stress can be generated by a source-level pinning layer that prevents vertical expansion of the vertical semiconductor channel. Vertical tensile stress can be induced by using a layer stack including polysilicon and a silicon-germanium alloy for the vertical semiconductor channel.