Sequential read mode static random access memory (SRAM)

The present disclosure relates to a structure including a sequential mode read controller which is configured to receive a sequential read enable burst signal and a starting word line address, identify consecutive read operations from an array of storage cells accessed via a plurality of word lines,...

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Bibliographic Details
Main Authors Hunt-Schroeder, Eric D, Patil, Akhilesh, Arsovski, Igor
Format Patent
LanguageEnglish
Published 06.10.2020
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Summary:The present disclosure relates to a structure including a sequential mode read controller which is configured to receive a sequential read enable burst signal and a starting word line address, identify consecutive read operations from an array of storage cells accessed via a plurality of word lines, precharge a plurality of bit lines of the storage cells no more than once during the consecutive read operations, and hold a word line of the word lines active throughout the consecutive read operations. The sequential read enable burst signal and a starting word line address are decoded to select a row address and activate the corresponding word line from a plurality of word lines in the array.
Bibliography:Application Number: US201816031439