System, method, and computer program product for generating a formal verification model

The present disclosure relates to a method for use in a formal verification of an electronic design. Embodiments may include receiving, using a processor, a specification model associated with an electronic design and generating, using a parser, an intermediate representation based upon, at least in...

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Bibliographic Details
Main Authors Farah, Habeeb, Chen, Benjamin Meng-Ching, Hanna, Ziyad, Mukherjee, Rajdeep
Format Patent
LanguageEnglish
Published 29.09.2020
Subjects
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
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Summary:The present disclosure relates to a method for use in a formal verification of an electronic design. Embodiments may include receiving, using a processor, a specification model associated with an electronic design and generating, using a parser, an intermediate representation based upon, at least in part, the specification model. Embodiments may also include applying a machine generated semantic preserving program transformation to the intermediate representation to create a semantically transformed specification model and synthesizing the semantically transformed specification model to generate a formal verification model.
Bibliography:Application Number: US201916434129