Optimizing branch re-wiring in a software instruction cache

A method includes a computer device receiving a branch instruction; the computer device managing two tables, where a first table relates to application blocks and a second table relates to available address slots; and the computer device calculating a target of the branch instruction using a branch-...

Full description

Saved in:
Bibliographic Details
Main Authors Bertolli, Carlo, O'Brien, John Kevin Patrick, Sura, Zehra Noman, Eichenberger, Alexandre E
Format Patent
LanguageEnglish
Published 22.09.2020
Subjects
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
Online AccessGet full text

Cover

More Information
Summary:A method includes a computer device receiving a branch instruction; the computer device managing two tables, where a first table relates to application blocks and a second table relates to available address slots; and the computer device calculating a target of the branch instruction using a branch-to-link register, the computer device optimizes re-wiring in a cache using the calculation and the managed two tables.
Bibliography:Application Number: US201514712253