Semiconductor device, memory test method for semiconductor device, and test pattern generation program

To overcome a problem of increase of test time related to BIST in a conventional semiconductor device, a semiconductor device according to one embodiment includes a plurality of memory arrays having different sizes, a test pattern generation circuit that outputs a test pattern for the memory arrays,...

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Bibliographic Details
Main Authors Saito, Tatsuya, Ueki, Takeshi, Maeno, Hideshi, Sasaki, Tomonori
Format Patent
LanguageEnglish
Published 15.09.2020
Subjects
INFORMATION STORAGE
MEASURING
MEASURING ELECTRIC VARIABLES
MEASURING MAGNETIC VARIABLES
PHYSICS
STATIC STORES
TESTING
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Summary:To overcome a problem of increase of test time related to BIST in a conventional semiconductor device, a semiconductor device according to one embodiment includes a plurality of memory arrays having different sizes, a test pattern generation circuit that outputs a test pattern for the memory arrays, and a memory interface circuit that is provided for every memory array and converts an access address. The memory interface circuit shifts a test address output from the test pattern generation circuit in accordance with a shift amount set for every memory array, thereby converting the test address to an actual address of a memory array to be tested.
Bibliography:Application Number: US201916378056