Stacked indium gallium arsenide nanosheets on silicon with bottom trapezoid isolation

• Main Authors: Khojasteh, Mahmoud, Reznicek, Alexander, Hashemi, Pouya, Ando, Takashi
• Format: Patent
• Language: English
• Published: 18.08.2020
• Subjects: BASIC ELECTRIC ELEMENTS; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR; ELECTRICITY; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; NANOTECHNOLOGY; PERFORMING OPERATIONS; SEMICONDUCTOR DEVICES; SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; TRANSPORTING

A method of forming a nanosheet semiconductor device that includes epitaxially forming a stack of at least two repeating nanosheets, the at least two repeating nanosheets including a first nanosheet layer of a first III-V semiconductor material and a second nanosheet layer of a second III-V semiconductor material. A sacrificial gate structure is formed on the stack of the at least two repeating nanosheets. Source and drain regions are epitaxially formed on the second nanosheet layer. The sacrificial gate structure is removed to provide a gate opening. An etch process removes the first nanosheet layer selectively to the second nanosheet layer, wherein the etch process is selective to facets of the material for the first nanosheet layer to provide an inverted apex at the base of the stack. A dielectric layer is deposited filling the inverted apex. A functional gate structure is formed in the gate opening.