Interconnected integrated circuit (IC) chip structure and packaging and method of forming same

• Main Authors: Kuemerle, Mark W, Polomoff, Nicholas A, Nayak, Jawahar P, Sauter, Wolfgang, Stone, David B, Parent, Eric S, Choi, Seungman, Tremble, Eric W
• Format: Patent
• Language: English
• Published: 14.07.2020
• Subjects: BASIC ELECTRIC ELEMENTS; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR; ELECTRICITY; SEMICONDUCTOR DEVICES

An IC chip structure including a plurality of IC chips electrically connected to one another in back-end-of-line (BEOL) interconnect layer of the structure is disclosed. The IC structure may include openings in crack-stop structures surrounding the IC chips and a interconnect wire extending between the IC chips through the openings. A packaging structure for utilizing the IC structure where at least one IC chip is inoperable is also disclosed. The structure may include a first bond pad array on a top surface of a packaging substrate including operable bond pads connected to an operable IC chip and structural support bond pads connected to the inoperable IC chip; a second bond pad array on a bottom surface of the substrate including operable bond pads connected to a single IC chip printed circuit board; and an interconnect structure for connecting the operable bond pads of the first and second bond pad arrays.