Device, system and method for providing on-chip test/debug functionality

Techniques and mechanisms for providing on-chip link control functionality to facilitate emulation of a communication. In an embodiment, an integrated circuit (IC) chip includes a physical layer (PHY) which supports communication compatible with a high-speed serial interface standard. A link control...

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Bibliographic Details
Main Authors Pappu, Lakshminarayana, Bhatt, Suketu U, Chellappan, Satheesh
Format Patent
LanguageEnglish
Published 07.07.2020
Subjects
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
MEASURING
MEASURING ELECTRIC VARIABLES
MEASURING MAGNETIC VARIABLES
PHYSICS
TESTING
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Summary:Techniques and mechanisms for providing on-chip link control functionality to facilitate emulation of a communication. In an embodiment, an integrated circuit (IC) chip includes a physical layer (PHY) which supports communication compatible with a high-speed serial interface standard. A link controller of the IC chip is coupled between the PHY and an interconnect architecture which variously couples a host and other resources of the IC chip to each other. A test controller of the IC chip signals a test mode to implement a loopback path of the link controller in lieu of one or more functional paths for communication with the PHY. In another embodiment, signal output by the loopback path emulate a communication from a resource other than the test controller.
Bibliography:Application Number: US201615394666