Reduced resistance source and drain extensions in vertical field effect transistors

Semiconductor devices and methods of forming the same include forming first charged spacers on sidewalls of a semiconductor fin. A gate stack on the fin is formed over the first charged spacers. Second charged spacers are formed on sidewalls of the fin above the gate stack. The fin is recessed to a...

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Bibliographic Details
Main Authors Zhang, Chen, Yeung, Chun W, Xu, Peng
Format Patent
LanguageEnglish
Published 30.06.2020
Subjects
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
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Summary:Semiconductor devices and methods of forming the same include forming first charged spacers on sidewalls of a semiconductor fin. A gate stack on the fin is formed over the first charged spacers. Second charged spacers are formed on sidewalls of the fin above the gate stack. The fin is recessed to a height below a top level of the second charged spacers.
Bibliography:Application Number: US201916276118